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preliminary technical information AD7889 a lc 2 mos single supply, 12-bit 600 ksps adc functional block diagram product highlights 1. the AD7889 features a conversion time of 1.4s (mode a) and a track/hold acquisition time of 300ns. this allows a throughput rate for the part up to 600?ksps. modes c and d can be used to allow a throughput rate of 500ksps. 2. the AD7889 operates from a single +5?v supply and con- sumes 60?mw typ making it ideal for low power and por- table applications. 3. the part offers a high speed, serial interface for easy connec- tion to microprocessors, microcontrollers and digital signal processors. general description the AD7889 is a high speed, low power, 12-bit a/d converter that operates from a single +5?v supply. the part contains a successive approximation adc, an on-chip track/hold ampli- fier, an internal +2.5?v reference and on-chip versatile interface structures that allows serial communication to a microprocessor in a variety of operating modes. the part accepts an analog input range of 10?v or 5?v (AD7889-1), 0 v to +2.5?v or 0 v to +5v (AD7889-2) and 2.5?v (AD7889-3). overvoltage protection on the analog inputs for the AD7889-1 and AD7889-3 allows the input voltage to go to 17 v or 7 v respectively without damaging the ports. the AD7889 offers a choice of serial interface modes which al- lows direct connection to the serial ports of microcontrollers and digital signal processors. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the part is also specified for dynamic performance parameters including harmonic dis- tortion and signal-to-noise ratio. the AD7889 is fabricated in analog devices? linear compat- ible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low power cmos logic. it is available in a 16-pin, ssop. ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. features fast 12-bit adc with 1.4 s conversion time up to 600 ksps throughput rate (mode a) single supply operation on-chip track/hold amplifier selection of input ranges: 10 v or 5 v for AD7889-1 0 v to +2.5 v or 0v to+5 v for AD7889-2 2.5 v for AD7889-3 high speed serial interface low power, 60 mw typ v ref v dd +2.5v reference 2?k 12-bit adc track /hold signal scaling AD7889 dgnd agnd v in1 v in2 rfs sclk sdata standby control logic contclk 16/14b convst
(v dd = +5 v 5%, agnd = dgnd = 0 v, ref in = +2.5 v. all specifications t min to t max unless otherwise noted.) AD7889?specifications parameter a versions 1 b versions s version 2 units test conditions/comments dynamic performance AD7889-1, AD7889-2 f in = 100 khz. f sample = 500 ksps signal to (noise + distortion) ratio 3 70 70 70 db min total harmonic distortion 3 ?80 ?80 ?78 db max peak harmonic or spurious noise 3 ?81 ?81 ?79 db max intermodulation distortion 3 fa = 49?khz, fb = 50?khz 2nd order terms ?80 ?80 ?78 db max 3rd order terms ?80 ?80 ?78 db max AD7889-3 f in = 100 khz. f sample = 600 ksps signal to (noise + distortion) ratio 3 70 70 db min total harmonic distortion 3 ?78 ?78 db max peak harmonic or spurious noise 3 ?79 ?79 db max intermodulation distortion 3 fa = 49?khz, fb = 50?khz 2nd order terms ?78 ?78 db max 3rd order terms ?78 ?78 db max dc accuracy resolution 12 12 12 bits minimum resolution for which no missing codes are guaranteed 12 12 12 bits relative accuracy 3 1 1 lsb max differential nonlinearity 3 1 1 lsb max positive full-scale error 3 4 4 5 lsb max AD7889-1 negative full-scale error 3 4 4 5 lsb max bipolar zero error 3 3 2 3 lsb max AD7889-3 negative full-scale error 3 4 4 lsb max bipolar zero error 3 4 3 lsb max AD7889-2 only unipolar offset error 3 4 3 4 lsb max analog input AD7889-1 input voltage range 10 10 10 volts input applied to v in1 with v in2 grounded input voltage range 5 5 5 volts input applied to v in1 and v in2 input resistance 25 25 25 k w min input applied to v in1 with v in2 grounded AD7889-2 input voltage range on v in1 0 to +5 0 to +5 0 to +5 volts input applied to v in1 with v in2 grounded input voltage range on v in1 0 to +2.5 0 to +2.5 0 to +2.5 volts input applied to v in1 and v in2 input current 10 10 50 na max AD7889-3 input voltage range on v in1 2.5 2.5 volts input applied to v in1 input resistance 2 2 k w min reference output/input vref input voltage range 2.375/2.625 2.375/2.625 2.375/2.625 v min/v max 2.5 v 5% input impedance 1.6 1.6 1.6 k w min resistor connected to internal reference node input capacitance 4 10 10 10 pf max vref output voltage 2.5 2.5 2.5 v nom vref error @ +25c 10 10 10 mv max t min to t max 20 20 25 mv max vref temperature coefficient 25 25 25 ppm/c typ vref output impedance 5.5 5.5 5.5 k w nom logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 a max v in = 0 v to v dd input capacitance, c in 4 10 10 10 pf max rev. b prelim. 7/97 2
AD7889 rev. b prelim. 7/97 ?3? preliminary technical information absolute maximum ratings* (t a = +25c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . ?0.3?v to +7?v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . ?0.3?v to +7?v analog input voltage to agnd AD7889-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17?v AD7889-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v AD7889-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v reference input voltage to agnd . . ?0.3 v to v dd + 0.3?v digital input voltage to dgnd . . . . . ?0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . ?0.3 v to v dd + 0.3 v operating temperature range commercial (a, b versions) . . . . . . . . . . . ?40c to +85c extended (s version) . . . . . . . . . . . . . . . ?55c to +125c storage temperature range . . . . . . . . . . . . ?65c to +150c parameter a versions 1 b versions s version 2 units t est conditions/comments logic outputs output high voltage, v oh 4.0 4.0 4.0 v min i source = 200 a output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma floating-state leakage current 10 10 10 a max floating-state capacitance 4 15 15 15 pf max output coding AD7889-1 and AD7889-3 2s complement AD7889-2 straight (natural) binary conversion rate conversion time 1.4 1.4 s max mode a conversion time 1.6 1.6 s max modes c and d conversion time 2.4 2.4 s max mode b track/hold acquisition time 3 0.3 0.3 s max all modes power requirements v dd +5 +5 +5 v nom 5% for specified performance i dd 5 normal operation 18 18 19 ma max standby mode 6 AD7889-1, AD7889-2 250 250 15 a typ AD7889-3 40 40 a max power dissipation 5 normal operation 90 90 95 mw max v dd = +5 v. typically 60?mw standby mode 6 AD7889-1, AD7889-2 1.25 1.25 0.075 mw typ AD7889-3 200 200 w max v dd = +5 v. typically 50?w notes 1 temperature ranges are as follows: a, b versions: ?40c to +85c; s version: ?55c to +125c. 2 s version available on AD7889-1 and AD7889-2 only. 3 see terminology. 4 sample tested @ +25c to ensure compliance. 5 these normal mode and standby mode currents are achieved with resistors (in the range 10 k w to 100 k w ) to either dgnd or v dd on pins x, x, x and x. 6 a conversion should not be initiated on the part within 30 s of exiting standby mode. specifications subject to change without notice. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150c ssop package, power dissipation. . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220c * stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD7889 ?4? rev. b prelim. 7/97 preliminary technical information timing characteristics 1, 2 a, b s parameter versions version units test conditions/comments t conv 1.4 s max conversion time for AD7889 (mode a) 1.6 1.6 s max conversion time for AD7889 (modes c &d) t acq 300 ns min acquisition time for AD7889 serial interface t 1 3 20 20 ns min sclk rising edge to data valid hold time t 2 3 30 35 ns min rfs low to sclk falling edge setup time t 3 25 25 ns min sclk high pulse width t 4 25 25 ns min sclk low pulse width t 5 xx xx ns min convst high to sclk falling edge t 6 20 20 ns min sclk rising edge to rfs rinsing edge t 8 25 25 ns max sclk high pulse width (mode b) t 9 25 25 ns min sclk low pulse width (mode b) t 10 xx xx ns min convst high to rfs falling edge notes 1 sample tested at +25c to ensure compliance. all input signals are measured with tr = tf = 1 ns (10% to 90% of +5 v) and timed from a voltage level of +1.6?v. 2 see figures 2a - 2d. 3 measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8?v or 2.4?v. specifications subject to change without notice. figure 1. load circuit for access time and bus relinquish time caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7889 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (v dd = +5?v 5%, agnd = dgnd = 0?v, ref in = +2.5?v) 1.6ma +1.6v 200a 50pf to output pin
AD7889 rev. b prelim. 7/97 ?5? preliminary technical information pin configuration ssop v in2 v in1 av dd vref agnd standby rfs sdata agnd contclk 16/14b idlehi convst dgnd dv dd sclk 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AD7889 top view (not to scale) ordering guide input sample relative temperature package model range rate accuracy range option 1 AD7889ars-1 5 v or 10 v 600 ksps ?40c to +85c rs-16 AD7889brs-1 5 v or 10 v 600 ksps 1 lsb ?40c to +85c rs-16 AD7889ars-2 0 v to 2.5 v or 0 v to 5 v 500 ksps ?40c to +85c rs-16 AD7889ars-3 2.5 v 500 ksps 1 lsb ?40c to +85c rs-16 eval-AD7889-1cb 2 evaluation board eval-AD7889-2cb 2 evaluation board eval-AD7889-3cb 2 evaluation board eval-control board 3 controller board notes 1 r s= ssop. 2 these boards can be used as stand-alone evaluation boards or in conjunction with the eval-control board for evaluation/demonstr ation purposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices? evaluation boards ending in the cb designators.
AD7889 ?6? rev. b prelim. 7/97 preliminary technical information pin function description pin no. mnemonic description 1v in2 analog input 2. for the AD7889-1, this input either connects to agnd or to v in1 to determine the analog input voltage range. with v in2 connected to agnd on the AD7889-1, the analog in- put range at the v in1 input is 10?v. with v in2 connected to v in1 on the AD7889-1, the analog input range to the part is 5?v. with v in2 connected to agnd on the AD7889-2, the analog input range at the v in1 input is 0 v to +5?v. with v in2 connected to v in1 on the AD7889-2, the analog input range to the part is 0?v to +2.5 v. for theAD7889-3, this input can be left unconnected but must not be connected to a potential other than agnd. 2v in1 analog input 1. the analog input voltage to be converted by the AD7889 is applied to this input. for the AD7889-1, the input voltage range is either 5?v or 10?v depending on where the v in2 input is connected. for the AD7889-2, the voltage range on the v in1 input is 0 v to +2.5?v or 0 v to +5 v with respect to the voltage appearing at the v in2 input. for the AD7889-3, the voltage range on the v in1 input is 2.5?v. 3av dd positive supply voltage, +5v 5%. 4 vref voltage reference input. an external reference source should be connected to this pin to provide the reference voltage for the AD7889s conversion process. the nominal reference voltage for the AD7889 is 2.5v. 5 agnd analog ground. ground reference for analog circuitry. 6 standby standby input. logic input. with this input at a logic high, the part is in its normal operating mode; with this input at a logic low the part is placed in its standby or power-down mode, which reduces power comsumption to 5mw typical. 7 rfs receive frame synchronization. digital output. this signal goes low for the duration of valid output data. 8 sdata serial data. logic output. serial data is provided on this pin when rfs is low. 9 sclk serial clock. logic input/output. this pin is used to clock serial data from the AD7889. the pin can be either an input or an output depending on which interface mode is used. the interface mode is selected by the 16/14b and contclk pins. 10 dv dd positive supply voltage for digital logic, +5 v 5%. 11 dgnd digital ground. ground reference for digital circuitry. 12 convst convert start. logic input. a low to high transition on this input puts the track/hold into its hold mode and starts conversion. 13 idlehi idle high. level triggered input. this input controls the idle state of the serial clock. with the in- put high, data should be latched on the falling edge of sclk. with the input low, data should be latched on the rising edge of sclk. 14 16/14b 16 clock/14 clock. digital input. this input determines how many clock cycles will be used to complete a conversion. if the input is high the AD7889 will take 16 clock cycles to complete a conversion. if the input is low the AD7889 will take 14 clock cycles to complete a conversion. 15 contclk continuous clock. digital input. this input tells the AD7889 whether a continuous or burst se- rial clock is being used. when the input is high the AD7889 expects to receive a continuous serial clock. when the input is low the AD7889 expects to receive either a burst of 16 or 14 serial clocks (depending on the state of 16/14b). 16 agnd analog ground. ground reference for analog circuitry.
AD7889 rev. b prelim. 7/97 ?7? preliminary technical information lation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the indi- vidual distortion products to the rms amplitude of the funda- mental expressed in dbs. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. positive full-scale error (AD7889-1) this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 ref in ? 3/2?lsb (10?v range) or 2 ref in ? 3/2?lsb (5?v range) after the bipo- lar zero error has been adjusted out. positive full-scale error (AD7889-2) this is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal ref in ? 3/2?lsb (0v to2.5v range) or 2 ref in ? 3/2?lsb (0v to 5v range) after the unipolar offset error has been adjusted out. positive full-scale error (AD7889-3) this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (ref in ? 3/2?lsb) after the bipo- lar zero error has been adjusted out. bipolar zero error (AD7889-1, AD7889-3) this is the deviation of the midscale transition (all 1s to all 0s) from the ideal (agnd ? 1/2?lsb). unipolar offset error (AD7889-2) this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal (agnd + 1/2?lsb). negative full-scale error (AD7889-1) this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal ?4 ref?in + 1/2?lsb (10?v range) or ?2 ref?in + 1/2?lsb (5?v range) after bipolar zero error has been adjusted out. negative full-scale error (AD7889-3) this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal ? ref?in + 1/2?lsb after bipolar zero error has been adjusted out. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2?lsb, after the end of conversion (the point at which the track/hold returns to track mode). it also applies to situations where there is a step input change on the input voltage applied to the v in input of the AD7889. it means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to v in before starting another conversion, to ensure that the part operates to specification. terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms ampli- tude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s / 2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74?db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7889, it is de- fined as: thd ( db )= 20 log v 2 2 +v 3 2 +v 4 2 +v 5 2 +v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m , n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the sec- ond order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the AD7889 is tested using two input frequencies away from the bottom end of the input bandwidth. in this case, the sec- ond and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the sec- ond and third order terms are specified separately. the calcu-
AD7889 ?8? rev. b prelim. 7/97 preliminary technical information circuit description the AD7889 is a fast, 12-bit single supply a/d converter. it provides the user with signal scaling, track/hold, reference, a/d converter and versatile interface logic functions on a single chip. the signal scaling on the AD7889-1 allows the part to handle either 5?v or 10?v input signals while operating from a single +5?v supply. the AD7889-2 handles either a 0 v to +2.5 v or 0 v to +5.0 v analog input range, while signal scaling on the AD7889-3 allows it to handle 2.5?v input sig- nals when operating from a single supply. the part requires a +2.5?v reference which can be provided from the part?s own in- ternal reference or from an external reference source. conversion is initiated on the AD7889 by pulsing the convst input. on the rising edge of convst , the track/ hold goes from track mode to hold mode and the conversion sequence is started. at the end of conversion , the track/hold returns to tracking mode and the acquisition time begins. con- version times for the part are 1.4s(mode a) and 1.6 s (modes b-d) the track/hold acquisition time is 300?ns. this al- lows the AD7889 to operate at throughput rates up to 600?ksps. track/hold section the track/hold amplifier on the AD7889 allows the adc to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. the input bandwidth of the track/hold is greater than the nyquist rate of the adc even when the adc is oper- ated at its maximum throughput rate of 600?khz (i.e., the track/hold can handle input frequencies in excess of 300?khz). the track/hold amplifier acquires an input signal to 12-bit ac- curacy in less than 300?ns. the operation of the track/hold is essenti ally transparent to the user. the track/hold amplifier goes from its tracking mode to its hold mode on the rising edge of convst . the aperture time for the track/hold (i.e., the delay time between the external convst signal and the track/hold actually going into hold) is typically 15?ns. at the end of conversion, the part returns to its tracking mode. the acquisition time of the track/hold amplifier begins at this point. reference section the AD7889 contains a single reference pin, labelled vref, which either provides access to the part?s own +2.5?v refer- ence or to which an external +2.5?v reference can be con- nected to provide the reference source for the part. the part is specified with a +2.5?v reference voltage. errors in the refer- ence source will result in gain errors in the AD7889?s transfer function and will add to the specified full-scale errors on the part. on the AD7889-1 and AD7889-3, it will also result in an offset error injected in the attenuator stage. the AD7889 contains an on-chip +2.5?v reference. to use this reference as the reference source for the AD7889, simply connect a 0.1?f disc ceramic capacitor from the vref pin to agnd. the voltage that appears at this pin is internally buff- ered before being applied to the adc. if this reference is re- quired for use external to the AD7889, it should be buffered as the part has a fet switch in series with the reference output resulting in a source impedance for this output of 5.5?k w nominal. the tolerance on the internal reference is 10?mv at 25c with a typical temperature coefficient of 25?ppm/c and a maximum error over temperature of 25?mv. if the application requires a reference with a tighter tolerance or the AD7889 needs to be used with a system reference, then the user has the option of connecting an external reference to this vref pin. the external reference will effectively overdrive the internal reference and thus provide the reference source for the adc. the reference input is buffered before being ap- plied to the adc with the maximum input current is 100?a. suitable reference sources for the AD7889 include the ad680, ad780 and ref43 precision +2.5?v references. interfacing the part has a versatile serial 3 wire interface with four modes of operation. the modes are selected using the contclk and 16/14b pins. the serial interface can be set up to use either a continuous or burst clock. with contclk at a logic 1 the AD7889 expects a continuous serial clock to be provided. with contclk at a logic 0 the AD7889 expects a burst serial clock to be provided. table i shows the interface modes available. table i. AD7889 interface modes interface mode 16/14b contclk mode a 0 0 mode b 0 1 mode c 1 0 mode d 1 1 figures 2a-2d show the timing diagrams for reading from the AD7889 in the various serial interface modes. rfs is driven low as the AD7889 outputs the data. mode a description. the AD7889 can be used in mode a by connecting contclk and 16/14b to logic 0. in this mode the AD7889 provides a burst sclk. the conversion is initiated by pulsing convst. 14 sclk pulses are provided to output the conver- sion result. after the first two rising edges of slck (assuming idlehi = 1) the rfs signal is asserted. the conversion result is available on the next 12 falling sclk edges. mode b description. the AD7889 can be used in mode b by connecting contclk to logic 1 and 16/14b to logic 0. in this mode the AD7889 expects a continuous sclk to be provided.the con- version is initiated by pulsing convst. the rfs signal is as- serted after the first rising edge of the sclk following a convst .the following 14 clock cycles contain the conver- sion result with the first two bits being don't cares.the 15th rising edge after the convst will bring the rfs back high. mode c description. the AD7889 can be used in mode c by connecting contclk to logic 0 and 16/14b to logic 1. in this mode the AD7889 expects a burst sclk to be provided.the conversion is initiated by pulsing convst. the rfs signal is then as- serted and 16 serial clocks should be provided. the conversion result will be valid on the falling edges of the 16 clock cycles (assuming idlehi = 1 ). when the clock returns to its idle state (dependent on idlehi) the rfs will return high.
AD7889 rev. b prelim. 7/97 ?9? preliminary technical information db3 db2 db1 db0 sclk (o) convst ( i ) sdata (o) db10 db11 xx xx rfs (o) 12 34 14 13 12 11 5 t 1 t 2 t 3 t 4 t 5 t 6 db3 db3 db2 db2 db1 db1 db0 db0 sclk (i) convst ( i ) sdata (o) db10 db10 db11 db11 xx xx xx xx rfs (o) 1234 14 13 12 11 5 t 9 t 8 db3 db3 db2 db2 db1 db1 db0 db0 sclk (i) convst ( i ) sdata (o) db10 db10 db11 db11 rfs (o) 1234 16 15 14 13 56 7 t 10 t 3 t 4 db3 db3 db2 db2 db1 db1 db0 db0 sclk (i) convst ( i ) sdata (o) db10 db10 db11 db11 frame (o) 1234 16 15 14 13 56 7 figure 3a. mode a timing diagram (idlehi=1) figure 3b. mode b timing diagram (idlehi=1) figure 3c. mode c timing diagram (idlehi=1) figure 3d. mode d timing diagram (idlehi=1)
AD7889 ?10? rev. b prelim. 7/97 preliminary technical information analog input section the AD7889 is offered as three part types allowing for five different analog input voltage ranges. the AD7889-1 handles either 5?v or 10?v input voltage ranges. the AD7889-2 handles either 0 v to +2.5?v or 0 v to +5 v input voltage ranges while the AD7889-3 handles an input range of 2.5?v. AD7889-1 figure 3 shows the analog input section for the AD7889-1. the analog input range is pin-strappable (using v in2 ) for either 5?v or 10?v on the v in1 input. with v in2 connected to agnd, the input range on v in1 is 10?v, and the input resis- tance on v in1 is 25 k w nominal. with v in2 connected to v in1 , the input range on v in1 is 5?v, and the input resistance on v in1 is 15k w nominal. as a result, the v in1 and v in2 inputs should be driven from a low impedance source. the resistor at- tenuator stage is followed by the high input impedance stage of the track/hold amplifier. this resistor attenuator stage allows the input voltage to go to 17 v without damaging the AD7889-1. table ii. ideal input/output code table for the AD7889-1 digital output analog input code transition +fsr/2 ? 3/2 lsb 1, 2 (9.99268 or 4.99634) 3 011 . . . 110 to 011 . . . 111 +fsr/2 ? 5/2 lsbs (9.98779 or 4.99390) 011 . . . 101 to 011 . . . 110 +fsr/2 ? 7/2 lsbs (9.98291 or 4.99146) 011 . . . 100 to 011 . . . 101 agnd + 3/2 lsb (0.00732 or 0.00366) 000 . . . 001 to 000 . . . 010 agnd + 1/2 lsb (0.00244 or 0.00122) 000 . . . 000 to 000 . . . 001 agnd ? 1/2 lsb (?0.00244 or ?0.00122) 111 . . . 111 to 000 . . . 000 agnd ? 3/2 lsb (?0.00732 or ?0.00366) 111 . . . 110 to 111 . . . 111 ?fsr/2 + 5/2 lsb (?9.98779 or ?4.99390) 100 . . . 010 to 100 . . . 011 ?fsr/2 + 3/2 lsb (?9.99268 or ?4.99634) 100 . . . 001 to 100 . . . 010 ?fsr/2 + 1/2 lsb (?9.99756 or ?4.99878) 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range and vref = +2.5 v, is 20 v for the 10 v range and 10 v for the 5 v range. 2 1 lsb = fsr/4096 = 4.88 mv (10 v range) and 2.44 mv (5 v range) with vref = +2.5 v. 3 10 v range or 5 v range. mode d description. the AD7889 can be used in mode d by connecting contclk and 16/14b to logic 1. in this mode the AD7889 expects a continuous sclk to be provided.the conversion is initiated by pulsing convst. the first rising edge of the sclk following the convst causes the rfs to be as- serted. the conversion result is available on the next 16 falling edges of sclk (assuming idlehi = 1). the rfs returns back high on the rising edge following the last bit of data. +2.5 reference vref v in1 v in2 agnd to high impedance sha input to adc reference circuitry 2k w 5.5k w 22k w 11k w 22k w AD7889-2 figure 4 shows the analog input section for the AD7889-2. the analog input range is pin-strappable (using v in2 ) for either 0 v to +2.5 v or 0v to +5 v. with v in2 connected to agnd, the input range on v in1 is 0 v to +5 v, and the input resistance on v in1 is 11k w nominal. with v in2 connected to v in1 , the input range on v in1 is 0 v to 2.5 v, and the input resistance on v in1 is 2.75k w nominal. as a result, the v in1 and v in2 inputs should be driven from a low impedance source. the resistor attenuator stage is followed by the high input impedance stage of the track/hold amplifier. this resistor attenuator stage allows the input voltage to go to +7 v without damaging the AD7889-2. figure 3. AD7889-1 analog input structure the designed code transitions occur midway between succes- sive integer lsb values (i.e., 1/2?lsb, 3/2?lsbs, 5/2 lsbs). output coding is 2s complement binary with 1?lsb = fsr/ 4096 = 20?v/4096 = 4.88?mv for the 10?v range and 1?lsb = fsr/4096 = 10?v/4096 = 2.44?mv for the 5?v range. the ideal input/output transfer function for the AD7889-1 is shown in table ii. figure 4. AD7889-2 analog input structure once again, the designed code transitions occur midway be- tween successive integer lsb values (i.e., 1/2?lsb, 3/2?lsbs, 5/2 lsbs). output coding is straight (natural) binary with 1?lsb = fsr/4096 = 2.5?v/4096 = 0.61?mv, for the 0 v to 2.5v range and 1?lsb = fsr/4096 = 5?v/4096 = 1.22?mv, for the 0 v to 5v range. the ideal input/output transfer func- tion for the AD7889-2 is shown in table iii. +2.5 reference vref v in1 v in2 to high impedance sha input to adc reference circuitry 2k w 5.5k w 5.5k w agnd
AD7889 rev. b prelim. 7/97 ?11? preliminary technical information +fsr ? 5/2 lsbs (2.498474?v) 111 . . . 110 to 111 . . . 110 +fsr ? 7/2 lsbs (2.497864 v) 111 . . . 100 to 111 . . . 101 agnd + 5/2 lsb (0.001526?v) 000 . . . 010 to 010 . . . 011 agnd + 3/2 lsb (0.00916?v) 000 . . . 001 to 001 . . . 010 agnd + 1/2 lsb (0.000305?v) 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 5?v with vref = +2.5?v. 2 1?lsb = fsr/4096 = 1.22?mv (0v to +5v range) and 0.61 mv (0v to 2.5v range) with vref = +2.5 v. 3 fsr is full-scale range and is 2.5v with vref= +2.5 v. AD7889-3 figure 5 shows the analog input section for the AD7889-3. the analog input range is 2.5?v on the v in1 input. the v in2 input can be left unconnected but if it is connected to a poten- tial then that potential must be agnd. the input resistance on the v in1 is 2.75 k w nominal. as a result, the v in1 input should be driven from a low impedance source. the resistor at- tenuator stage is followed by the high input impedance stage of the track/hold amplifier. this resistor attenuator stage allows the input voltage to go to 7 v without damaging the AD7889-3. figure 6. AD7889 to adsp-21xx interface table iii. ideal input/output code table for the AD7889-2 digital output analog input code transition +fsr ? 3/2 lsb 1, 2 (4.998169?v) 111 . . . 110 to 111 . . . 111 +fsr ? 5/2 lsbs (4.996948?v) 111 . . . 110 to 111 . . . 110 +fsr ? 7/2 lsbs (4.995728 v) 111 . . . 100 to 111 . . . 101 agnd + 5/2 lsb (0.003052?v) 000 . . . 010 to 010 . . . 011 agnd + 3/2 lsb (0.01832?v) 000 . . . 001 to 001 . . . 010 agnd + 1/2 lsb (0.000610?v) 000 . . . 000 to 000 . . . 001 +fsr ? 3/2 lsb 2, 3 (2.499084?v) 111 . . . 110 to 111 . . . 111 +2.5 reference vref v in1 v in2 * agnd to high impedance sha input to adc reference circuitry 2k w 5.5k w 5.5k w v in2 * is unconnected internally on the AD7889-3 figure 5. AD7889-3 analog input structure the designed code transitions occur midway between succes- sive integer lsb values (i.e., 1/2?lsb, 3/2?lsbs, 5/2 lsbs). output coding is 2s complement binary with 1?lsb = fsr/ 4096 = 5?v/4096 = 1.22?mv with vref = +2.5?v. the ideal input/output transfer function for the AD7889-3 is shown in table iv. table iv. ideal input/output code table for the AD7889-3 digital output analog input code transition +fsr/2 ? 3/2 lsb 1, 2 (2.49817) 011 . . . 110 to 011 . . . 111 +fsr/2 ? 5/2 lsbs (2.49695) 011 . . . 110 to 011 . . . 110 +fsr/2 ? 7/2 lsbs (2.49573) 011 . . . 110 to 011 . . . 101 agnd + 3/2 lsb (0.00183) 000 . . . 001 to 000 . . . 010 agnd + 1/2 lsb (0.00061) 000 . . . 000 to 000 . . . 001 agnd ? 1/2 lsb (?0.00061) 111 . . . 111 to 000 . . . 000 agnd ? 3/2 lsb (?0.00183) 111 . . . 110 to 111 . . . 111 ?fsr/2 + 5/2 lsb (?2.49695) 100 . . . 010 to 100 . . . 011 ?fsr/2 + 3/2 lsb (?2.49817) 100 . . . 001 to 100 . . . 010 ?fsr/2 + 1/2 lsb (?2.49939) 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range and is 5?v with vref = +2.5?v. 2 1?lsb = fsr/4096 = 1.22?mv with vref = +2.5 v. microprocessor interfacing the AD7889 features a high speed serial interfaces with four modes of operation, allowing considerable flexibility in inter- facing to microprocessor systems. figures 6, 7 and 8 show some typical interface circuits between the AD7889 and popular dsp processors. the convst signal can be generated by a flag pin from the dsp or by external hardware controlled by a timer. AD7889 to adsp-21xx interface figure 6 shows a serial interface between the AD7889 and the adsp-21xx family of dsp processors. theAD7889 is operat- ing in mode a (maximum throughput) and the rfs and sclk signals are inputs to the dsp. the flag pin fl0 (con- trolled by an internal timer routine) is used to provide the convst . pulsing convst starts conversion and data is provided on the subsequent clock edges. . AD7889 convst rfs sdata sclk adsp-21xx rfs0 dr0 sclk0 fl0
AD7889 ?12? rev. b prelim. 7/97 preliminary technical information AD7889 to tms320c20 interface figure 7 shows the interface between the AD7889 (again in mode a) and the tms320c20 dsp processor. here a timer is used to generate the convst pulse to ensure equidistant sam- pling. for the tms320c20 the clkx, clkr, fsx and fsr should all be configured as inputs. the clkx and clkr should be connected together as should the fsx and fsr. AD7889 convst rfs sdata sclk tms320c20 fsx fsr clkr clkx dr timer figure7. AD7889 to tms320c20 interface AD7889 to dsp56000 interface figure 8 shows the interface between the AD7889 and the dsp56000 dsp processor.again a timer is used to start con- version and the data is clocked on the subsuquent clock edges. AD7889 convst rfs sdata timer sclk dsp56000 sc1 srd sck figure 8. AD7889 to dsp56000 interface grounding and layout the analog and digital supplies to the AD7889 are indepen- dent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part exhibits good immu nity to noise on the supplies but care must still be taken with regard to grounding and layout especially when using switching mode supplies. the printed circuit board which houses the AD7889 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes which can be separated easily. a mini- mum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the AD7889 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the AD7889. if the AD7889 is in a system where mul- tiple devices require agnd to dgnd connections, the con- nection should still be made at one point only, a star ground point which should be established as close as possible to the AD7889. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7889 to avoid noise coupling. the power supply lines to the AD7889 should use as large a trace as possible to provide low impedance paths and reduce the ef- fects of glitches on the power supply line. fast switching sig- nals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is important when using high resolution adcs. all analog supplies should be decoupled with 10?f tantalum in parallel with 0.1?f capacitors to agnd. to achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the de- vice. all logic chips should be decoupled with 0.1?f disc ceramic capacitors to dgnd.in systems where a common supply is used to drive both the av dd and dv dd of the AD7889, it is recommended that the systems avdd supply is used. in this case there should be a 10 w resistor between the av dd pin and dv dd pin. this supply should have the recom- mended analog supply decoupling capacitors between the v dd pin of the AD7889 and agnd and the recommended digital supply decoupling capacitor between the v dd pin of the AD7889 and dgnd. evaluating the AD7889 performance the recommended layout for the AD7889 is outlined in the evaluation board for the AD7889. the evaluation board pack- age includes a fully assembled and tested evaluation board, documentation and software for controlling the board from a pc using the eval-control board. the eval- control board can be used in conjunction with the AD7889 evaluation board, as well as many other analog de- vices evaluation boards ending in the cb designator. using the eval-control board with the AD7889 evaluation board allows the user to evaluate the ac and dc performance of the AD7889 on a pc. the software provided with the evaluation board allows the user to perform ac (fast fourier transform) and dc (histo- gram of codes) tests on the AD7889. the evaluation board can also be used in a stand-alone fashion without the eval-con- trol board but in this case, the user has to write their own software to evaluate the part. there are three versions of the evaluation board available, one for the AD7889-1, one for the AD7889-2 and one for the AD7889-3. the order numbers for the evaulation boards are eval-AD7889-1cb, eval- AD7889-2cb and eval-AD7889-3cb.

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